Design methodology for full custom CMOS microcomputers

A highly structured design methodology is necessary to be successful in the design of VLSI integrated circuits with more than 100000 transistors on a chip. Such a methodology is described: it is based on the regularity of the circuit architecture with an associated chip floor plan and on a new layout technique named metal oriented layout. This methodology has been tested with the design of a 13500 MOS microcomputer. From the instruction set and through different levels of instruction interpretation, the architecture and associated chip floor plan are generated. The detailed logic design is made directly in symbolic layout with the chip floor plan in mind. The proposed design methodology can be best appreciated by the short development time and small chip area required for the designed 13500 MOS microcomputer.

[1]  Monika Obrebska.  Efficiency and performance comparison of different design methodologies for control parts of microprocessors , 1982 .

[2]  Christopher R. Clare.  Designing logic systems using state machines , 1973 .

[3]  F. Anceau,et al.  Complex integrated circuit design strategy , 1982 .

[4]  C. Piguet,et al.  Automatic Generation of Metal Oriented Layout for CMOS Logic , 1983, ESSCIRC '83: Ninth European Solid-State Circuits Conference.

[5]  J. Zahnd,et al.  Basic Design Methods for CMOS Logic Circuits with Ordered Layout , 1983, ESSCIRC '83: Ninth European Solid-State Circuits Conference.

[6]  A.D. Lopez,et al.  A dense gate matrix layout method for MOS VLSI , 1980, IEEE Transactions on Electron Devices.

[7]  Raymond T. Boute,et al.  The binary decision machine as programmable controller , 1976 .

[8]  D. Aubert,et al.  Computer Aided Layout of Distributed CMOS Static Decoders , 1982, ESSCIRC '82: Eighth European Solid-State Circuits Conference.

[9]  M. Shima.  Solid state/computers: Demystifying microprocessor design: Big chips require artful compromises, as demonstrated by this design case history , 1979, IEEE Spectrum.

[10]  Carlo H. Séquin,et al.  A RISCy approach to VLSI , 1982, CARN.

[11]  J.W. Beyers,et al.  A 32-bit VLSI CPU chip , 1981, IEEE Journal of Solid-State Circuits.

[12]  Sung Mo Kang,et al.  Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..