Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

Three cross sections (rectangular, bullet shaped, and triangular), resulting from the fabrication process, of nanoscale In<sub>0.53</sub>Ga<sub>0.47</sub>As-on-insulator FinFETs with a gate length of 10.4 nm are modeled using in-house 3-D finite-element density-gradient quantum-corrected drift–diffusion and Monte Carlo simulations. We investigate the impact of the shape on <inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics and on the variability induced by metal grain granularity (MGG), line-edge roughness (LER), and random dopants (RDs) and compared with their combined effect. The more triangular the cross section, the lower the OFF-current, the drain-induced-barrier-lowering, and the subthreshold slope. The <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio is three times higher for the triangular-shaped FinFET than for the rectangular-shape one. Independent of the cross section, the MGG variations are the preeminent fluctuations affecting the FinFETs, with four to two times larger <inline-formula> <tex-math notation="LaTeX">$\sigma {V}_{T}$ </tex-math></inline-formula> than that from the LER and the RDs, respectively. However, the variability induced threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula>) shift is minimal for the MGG (around 2 mV), but <inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> shift increases 4-fold and 15-fold for the LER and the RDs, respectively. The cross-sectional shape has a very small influence in <inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> and OFF-current of the MGG, LER, and RD variabilities, both separated and in combination, with standard deviation differences of only 4% among the different device shapes. Finally, the statistical sum of the three sources of variability can predict simulated combined variability with only a minor overestimation.

[1]  Soha Hassoun,et al.  Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design , 2014, IEEE Transactions on Electron Devices.

[2]  K. Kalna,et al.  Statistical study of the influence of LER and MGG in SOI MOSFET , 2014 .

[3]  A. Asenov,et al.  Statistical Variability in Fully Depleted SOI MOSFETs Due to Random Dopant Fluctuations in the Source and Drain Extensions , 2012, IEEE Electron Device Letters.

[4]  K. Kalna,et al.  Study of Metal-Gate Work-Function Variation Using Voronoi Cells: Comparison of Rayleigh and Gamma Distributions , 2016, IEEE Transactions on Electron Devices.

[5]  Peter A. Markowich,et al.  The Stationary Semiconductor Device Equations. , 1987 .

[6]  K. Maitra,et al.  A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch , 2010, 2010 Symposium on VLSI Technology.

[7]  K. Kalna,et al.  Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs , 2016, IEEE Transactions on Electron Devices.

[8]  P. Kondekar,et al.  Fin shape dependent variability for strained SOI FinFETs , 2016 .

[9]  G. Patton.  Evolution and expansion of SOI in VLSI technologies: Planar to 3D , 2012, 2012 IEEE International SOI Conference (SOI).

[10]  Chi On Chui,et al.  Variability of Inversion-Mode and Junctionless FinFETs due to Line Edge Roughness , 2011, IEEE Electron Device Letters.

[11]  A. Asenov,et al.  Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study , 2011, IEEE Transactions on Electron Devices.

[12]  Chih-Hong Hwang,et al.  Effect of Fin Angle on Electrical Characteristics of Nanoscale Round-Top-Gate Bulk FinFETs , 2007, IEEE Transactions on Electron Devices.

[13]  Daniel Nagy,et al.  Scaling/LER study of Si GAA nanowire FET using 3D Finite Element Monte Carlo simulations , 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

[14]  Antonio J. Garcia-Loureiro,et al.  Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET , 2014, IEEE Transactions on Electron Devices.

[15]  Impact of intrinsic parameter fluctuations on the performance of HEMTs studied with a 3D parallel drift-diffusion simulator , 2007 .

[16]  Andrew R. Brown,et al.  Statistical variability and reliability in nanoscale FinFETs , 2011, 2011 International Electron Devices Meeting.

[17]  C. Merckling,et al.  An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[18]  K. Kalna,et al.  3D Finite Element Monte Carlo Simulations of Multigate Nanoscale Transistors , 2013, IEEE Transactions on Electron Devices.

[19]  K. Kalna,et al.  Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes , 2016 .

[20]  Priyanka,et al.  Impact of Fin Height and Fin Angle Variation on the Performance Matrix of Hybrid FinFETs , 2017, IEEE Transactions on Electron Devices.

[21]  K. Kalna,et al.  3D ‘atomistic’ simulations of dopant induced variability in nanoscale implant free In0.75Ga0.25As MOSFETs , 2012 .

[22]  Antonio J. García-Loureiro,et al.  Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  N. A. F. Othman,et al.  Performance and Device Design Based on Geometry and Process Considerations for 14/16-nm Strained FinFETs , 2016, IEEE Transactions on Electron Devices.