Low-power realization of FIR filters using current-mode analog design techniques

This work demonstrates the feasibility of low-power analog FIR filters using current-mode techniques. Preliminary results from the proposed filter indicate a power consumption that is much lower than alternate digital implementations at 20MSPS making it attractive for portable applications. The FIR filter comprises of a current-mode sample-and-hold configured as a delay element followed by an analog multiplier. Results from an 8-tap linear phase filter and a 16-tap non-linear phase filter are shown to match well with the ideal filter responses.

[1]  Tughrul Arslan,et al.  Architectural trade-offs in the design of low power FIR filtering cores , 2004 .

[2]  Dennis D. Buss,et al.  Transversal filtering using charge-transfer devices , 1973 .

[3]  David J. Allstot,et al.  Current-feedthrough effects and cancellation techniques in switched-current circuits , 1990, IEEE International Symposium on Circuits and Systems.

[4]  D. G. Nairn.  A high-linearity sampling technique for switched-current circuits , 1996 .

[5]  Gian Carlo Cardarilli,et al.  Power characterization of digital filters implemented on FPGA , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[6]  D.J. Allstot,et al.  FIR filtering using CMOS switched-current techniques , 1990, IEEE International Symposium on Circuits and Systems.

[7]  David V. Anderson,et al.  Cooperative analog-digital signal processing , 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[8]  Christofer Toumazou,et al.  n-step charge injection cancellation scheme for very accurate switched current circuits , 1994 .

[9]  John B. Hughes,et al.  S/sup 2/I: a two-step approach to switched-currents , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[10]  John B. Hughes,et al.  S2I: A Two-step Approach to Switched-Currents , 1993, ISCAS.

[11]  Venkatesh Srinivasan,et al.  A 531 nW/MHz, 128/spl times/32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).