Design and Comparative analysis of Thin Film Transistor

The downscaling variability, leakage, and performance saturation of conventional TFT technology has become a major concern. Now it has become increasingly difficult to meet transistor performance gain with reasonable device leakage, forcing the semiconductor industry to consider new transistor architectures. Hence, alternate device architectures are being explored which possess inherently better robustness to downscaling drawback of TFT. The objectives of present study is to design Bottom Gate TFT with SiO2 (50nm) and SiN (50nm) insulators with ZnO active materials and compare the transfer characteristics and output characteristics of SiO2 based TFT and SiN based TFT. The performance of the devices incorporating SiN, as measured by standard TFT parameters, was found to be superior to that of the SiO2 transistors. The threshold voltage shift of both sets of devices under gate bias stress was found to have logarithmic time dependence, indicating that charge trapping is the dominant instability mechanism. It is suggested that temporary charging and discharging of pre existing trap states within the band gap and band tails of the ZnO channel layer is responsible for the deterioration of these device parameters. The results suggest that the ZnO channel layer and/or the interface between the ZnO and the gate insulator layers are susceptible to charge trapping/defect formation instabilities due to lattice mismatch.