Time-range compatibility reasoning for asynchronous systems design

Abstract Many asynchronous systems are designed based on the successful operation of a handshake protocol for data transaction which meets the timing constraints imposed by different systems. For the practical case of the asynchronous bus operation of a micro-processor system, complex built-in mechanisms are developed to trigger various events to facilitate the operation of this protocol. With particular reference to the wait cycles insertion for a read cycle of the MC6800 microprocessor, we describe the general technique of time-range compatibility reasoning to capture the imprecise and complicated knowledge involved in diagnosing the correctness of a data transfer. An implementation using the expert system shell CLIPS illustrates how a simplified version of the proposed compatibility reasoning is used, together with the time-range constraint satisfaction and constraint propagation techniques previously developed, to solve the MC68000 read cycle problem which would otherwise be tackled only by human domain experts.

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