Power and Time Delay Analysis of Simple Comparator Implemented On Different Type of FPGA

In this particular work, we have implemented the algorithm of comparator on different version of FPGA like virtex-4, virtex-5, virtex-6, virtex-6(low power) and virtex-7. Using high performance Xilinx ISE software, we calculated the supply power and timing constraints like delay in timings from source pad to destination of the algorithm when implemented on different versions of FPGA.