Improvement method of the machine-model ESD robustness for a smart power IC

The failure behavior of the Smart Power IC using a 0.35 μm Bipolar-CMOS-DMOS was investigated, and the major ESD failure spots were found at the corner of the guard-ring structure and the high-voltage transistor, which is connected between the different power domains (Vdd-Vcc). The mechanism of these failures is investigated by the T-CAD simulation, and the method to improve the Machine Model (MM) Robustness is provided. To improve the MM level, the power rail was modified for blocking an unexpected ESD current path using the cost-effective metal revision. This increased MM ESD robustness significantly from 150V to 230V.

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