CAD TOOLS FOR POWER OPTIMIZATION - Sleep Transistor Insertion

A very popular approach for leakage power reduction is today represented by the adoption of emerging Multi Threshold CMOS (MTCMOS) technologies. They reduce stand-by power consumption by inserting a high-threshold cut-off MOSFET (i.e., a sleep transistor) in series to the initial low-threshold circuit. Hence, sub-threshold leakage current is reduced by the sleep transistor while performance loss is controlled. The latter happens thanks to two factors: First, the sleep transistor can be made very large (i.e., with low resistance), because it is shared among many cells; second, the large capacitance of the net connecting the cells and the sleep transistors provides a low-impedance AC discharge path, i.e., a virtual ground for the transient currents created by the switching gates. MTCMOS techniques present two drawbacks. First, they still require process modifications for supporting the high-threshold of the sleep MOSFET. Second, when a circuit is deactivated by power gating, it takes a non-negligible amount of time to wake up and reactivate it, simply because the large sleep transistor must be switched on and it must initially discharge the slow virtual ground capacitance. The first drawback can be eliminated if the sleep transistor is fabricated with the same threshold as the other transistors in the circuit. Even though leakage reduction is less substantial, the stacking effect still provides significant benefits. To address the second limitation, several sleep transistor approaches have been proposed, where multiple smaller sleep transistors are instantiated. The main advantage of sleep transistor insertion is having designs with a faster re-activation time when exiting the sleep state. However, the MTCMOS paradigm has found substantial application and positive results mostly in custom applications, e.g., microprocessors, where design and optimization is hand-crafted, while it is still seldom used in ASICs and SoCs, for which design is performed automatically through RTL-to-physical synthesis. Objective of the work was the development of a complete methodology for layout-aware, sleep transistor insertion for cell clusters that have physical proximity