RF and noise model of gate-all-around MOSFETs
暂无分享,去创建一个
[1] J. Barker,et al. On the physics and modeling of small semiconductor devices—I , 1980 .
[2] M. Omar,et al. Drift and diffusion of charge carriers in silicon and their empirical relation to the electric field , 1987 .
[3] C. Hu,et al. Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation , 1994 .
[4] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs , 2004 .
[5] M.J. Deen,et al. High-Frequency Noise of Modern MOSFETs: Compact Modeling and Measurement Issues , 2006, IEEE Transactions on Electron Devices.
[6] A. Cappy,et al. Noise modeling and measurement techniques (HEMTs) , 1988 .
[7] Y. Chen,et al. A Comparative Study of Double-Gate and Surrounding-Gate MOSFETs in Strong Inversion and Accumulation Using an Analytical Model , 2001 .
[8] J. P. Nougier,et al. Differential relaxation times and diffusivities of hot carriers in isotropic semiconductors , 1977 .
[9] A.S. Roy,et al. Noise modeling methodologies in the presence of mobility degradation and their equivalence , 2006, IEEE Transactions on Electron Devices.
[10] M. J. Deen,et al. Channel noise modeling of deep submicron MOSFETs , 2002 .
[11] Francois Danneville,et al. High frequency noise of SOI MOSFETs: performances and limitations (Invited Paper) , 2005, SPIE International Symposium on Fluctuations and Noise.
[12] B.C. Paul,et al. Modeling and optimization of fringe capacitance of nanoscale DGMOS devices , 2005, IEEE Transactions on Electron Devices.
[13] L. Selmi,et al. An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode , 2003 .
[14] Jean-Pierre Raskin,et al. Noise modeling in fully depleted SOI MOSFETs , 2004 .
[15] Antonio Lazaro,et al. A compact quantum model of nanoscale double-gate metal-oxide-semiconductor field-effect transistor for high frequency and noise simulations , 2006 .
[16] F. Danneville,et al. Compact-Modeling Solutions For Nanoscale Double-Gate and Gate-All-Around MOSFETs , 2006, IEEE Transactions on Electron Devices.
[17] N. Goldsman,et al. Efficient and accurate use of the energy transport method in device simulation , 1988 .
[18] G. O. Workman,et al. A process/physics-based compact model for nonclassical CMOS device and circuit design , 2004 .
[19] Meng-Hsueh Chiang,et al. Speed superiority of scaled double-gate CMOS , 2002 .
[20] B. Ryu,et al. High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[21] B. Iñíguez,et al. Continuous analytic I-V model for surrounding-gate MOSFETs , 2004, IEEE Electron Device Letters.
[22] A. Litwin,et al. Overlooked interfacial silicide-polysilicon gate resistance in MOS transistors , 2001 .
[23] A. Ziel. Noise in solid state devices and circuits , 1986 .
[24] F. Gamiz,et al. Modeling the Centroid and the Inversion Charge in Cylindrical Surrounding Gate MOSFETs, Including Quantum Effects , 2008, IEEE Transactions on Electron Devices.
[25] Kenji Taniguchi,et al. Analytical device model for submicrometer MOSFET's , 1991 .
[26] H. A. Hamid,et al. Explicit continuous model for long-channel undoped surrounding gate MOSFETs , 2005, IEEE Transactions on Electron Devices.
[27] D. Jimenez,et al. Modeling of nanoscale gate-all-around MOSFETs , 2004, IEEE Electron Device Letters.
[28] Jean-Pierre Raskin,et al. Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs , 2004 .
[29] Peter M. Asbeck,et al. A numerical Schrödinger–Poisson solver for radially symmetric nanowire core–shell structures , 2006 .
[30] A. Gnudi,et al. Low-Field Electron Mobility Model for Ultrathin-Body SOI and Double-Gate MOSFETs With Extremely Small Silicon Thicknesses , 2007, IEEE Transactions on Electron Devices.
[31] Antonio Lazaro,et al. RF and noise performance of double gate and single gate SOI , 2006 .
[32] Yuan Taur,et al. Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs , 2001 .
[33] Keunwoo Kim,et al. Double-gate CMOS: symmetrical- versus asymmetrical-gate devices , 2001 .
[34] Junji Koga,et al. Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs - Coulomb scattering, volume inversion, and /spl delta/T/sub SOI/-induced scattering , 2003, IEEE International Electron Devices Meeting 2003.
[35] Krishna C. Saraswat,et al. Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs , 2003 .
[36] Denis Flandre,et al. FinFET analogue characterization from DC to 110 GHz , 2005 .
[37] Kwangseok Han,et al. Analytical drain thermal noise current model valid for deep submicron MOSFETs , 2004 .
[38] C.C. Enz,et al. Compact modeling of thermal noise in the MOS transistor , 2005, IEEE Transactions on Electron Devices.
[39] Chris Hutchens,et al. High-frequency FinFET model , 2005 .
[40] G. Pei,et al. A physical compact model of DG MOSFET for mixed-signal circuit applications- part I: model description , 2003 .