Sense-Amplifier-Merged Comparator and Selector Scheme for BiCMOS Cache Memories

A novel circuit technique called a sense-amplifier-merged comparator and selector scheme for BiCMOS cache memories is developed. An ECL gate with an active PMOS load circuit is proposed and effectively applied in this scheme. The inherent high-speed and low-power nature of the circuit scheme is described in conjunction with attained performance of a test chip, which is designed and fabricated using a self-aligned 0.3 ¿m BiCMOS technology.

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