Three-tier PoP configuration utilizing flip chip Fan-in PoP bottom package

The increasing demand for functionality and performance in mobile handsets has driven the requirement for separate modem and application processors with requisite memory. PoP has helped reduce the footprint of each processor and memory package combination on the PCB. Stacking the processors and memory in a single three-tier PoP configuration would further reduce the footprint. This paper details the development of such a three-tier PoP configuration, utilizing Fan-in PoP technology for the bottom PoP. The developed three-tier PoP test vehicle successfully exhibited good surface mount yield and excellent board level drop test and temperature cycle performance.

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