Application of built in self-test for interconnect testing of FPGAs

Field Programmable Gate Arrays (FPGAs) are becoming more difficult to test due to their increasing complexity and density. Test methodologies for FPGAs consist of generating numerous configurations of programmable switches that connect wire segments to create signal flow paths. We have developed a system that takes an arbitrary FPGA interconnect network and automatically generates configurations for test. These configurations detect single stuck-at faults, pair-wise bridging faults and wire-open faults. We have modified the traditional FordFulkerson Max-Flow algorithm to enable the efficient definition of test configurations. The system also generates the bitstreams, programs the FPGA, and displays the result. We have tested a Xilinx Virtex XCV150 and have presented the number of configurations and the test time for the device.

[1]  Eric Keller.  JRoute: A Run-Time Routing API for FPGA Hardware , 2000, IPDPS Workshops.

[2]  Fabrizio Lombardi,et al.  Bridging fault detection in FPGA interconnects using IDDQ , 1998, FPGA '98.

[3]  Mehdi Baradaran Tahoori,et al.  Fault grading FPGA interconnect test configurations , 2002, Proceedings. International Test Conference.

[4]  Charles E. Stroud,et al.  Built-in self-test of FPGA interconnect , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[5]  Yervant Zorian,et al.  Different experiments in test generation for XILINX FPGAs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[6]  Yervant Zorian,et al.  Testing the Interconnect of RAM-Based FPGAs , 1998, IEEE Des. Test Comput..

[7]  P. Sundararajan,et al.  Testing FPGA Devices Using JBits , 2001 .

[8]  Y. Zorian,et al.  SRAM-based FPGA's: testing the LUT/RAM modules , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Charles E. Stroud,et al.  BIST-based diagnosis of FPGA interconnect , 2002, Proceedings. International Test Conference.

[10]  Fabrizio Lombardi,et al.  Detection of bridging faults in logic resources of configurable FPGAs using I/sub DDQ/ , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[11]  Russell Tessier,et al.  Testing and diagnosis of interconnect faults in cluster-based FPGA architectures , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Premachandran R. Menon,et al.  BIST-based delay path testing in FPGA architectures , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[13]  Steven A. Guccione,et al.  XBI: a Java-based interface to FPGA hardware , 1998, Other Conferences.

[14]  Shahin Toutounchi,et al.  FPGA test and coverage , 2002, Proceedings. International Test Conference.