Package-on-Package (PoP) for Advanced PCB Manufacturing Process

In the 1990's, both BGA (ball grid array) and CSP (chip size package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (surface mount device) from the 1980's and THD (through-hole mount device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability. Now, 3D packages are the next phase for its future use in advanced PCB manufacturing process. They can be classified into wafer level, chip level, and package level stacking. So, package-on-package (PoP), a type of 3D package level stacking, is to be discussed in this paper (Kada et al.)

[1]  Young-Gon Kim,et al.  Thermal performance characteristics of folded stacked packages , 2002, Eighteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings 2002 (Cat.No.02CH37311).

[2]  E. Ristolainen,et al.  Stacked thin dice packaging , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[3]  Telesphor Kamgaing,et al.  Future Package Technologies for Wireless Communication Systems , 2005 .

[4]  M. Karnezos,et al.  3D packaging: where all technologies come together , 2004, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).

[5]  M. Mantysalo,et al.  System design issues for 3D system-in-package (SiP) , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[6]  Young Gon Kim Folded stacked package development , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[7]  Ilyas Mohammed,et al.  A design and performance study of 3D packaging for high performance memory applications , 2003, IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003..

[8]  E. Ristolainen,et al.  Reliability evaluation of 3D-package with specific test structures , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[9]  Yuji Yano,et al.  Three-dimensional very thin stacked packaging technology for SiP , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[10]  F. Ferrando,et al.  Industrial flip-chip process for CSP-3D from design to manufacturing , 2000, Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146).

[11]  Young-Cheol Kim,et al.  The development of a novel stacked package: package in package , 2004, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).

[12]  C. S. Hsiao,et al.  Innovative stack-die package - S2BGA , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[13]  C.W.C. Lin,et al.  3D stacked packages with bumpless interconnect technology , 2003, IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003..

[14]  Andreas Ostmann,et al.  Realization of a stackable package using chip in polymer technology , 2002, 2nd International IEEE Conference on Polymers and Adhesives in Microelectronics and Photonics. POLYTRONIC 2002. Conference Proceedings (Cat. No.02EX599).