A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512

In Part One of this document we present some explanatory background discussion on VEST design and how we have approached the task of benchmarking VEST variants in relation to AES and SHA-2. Many of the issues we touch upon are well understood by semi-conductor design and synthesis engineers, but since the greater proportion of the readers are cryptographers skilled in software design, we consider it necessary and helpful to discuss these issues. One such issue is the constraints imposed on a cipher implementation by power-budgets and thermal issues.

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