Power modeling for high performance network-on-chip architectures

This paper has been temporarily withdrawn based on Publishers request. The reason for this withdrawal will be soon communicated by the publisher. The full Elsevier Policy on Article Withdrawal can be found at https://www.elsevier.com/about/our-business/policies/article-withdrawal .

[1]  Partha Pratim Pande,et al.  Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[2]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[3]  Partha Pratim Pande,et al.  Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[5]  Yaseer Arafat Durrani,et al.  Efficient power analysis approach and its application to system-on-chip design , 2016, Microprocess. Microsystems.

[6]  Partha Pratim Pande,et al.  Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs , 2004, GLSVLSI '04.

[7]  Mohamed A. Abd El-Ghany,et al.  High throughput architecture for high performance NoC , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[8]  Jun-Fa Mao,et al.  Global interconnect width and spacing optimization for latency, bandwidth and power dissipation , 2005 .

[9]  Li-Shiuan Peh,et al.  SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Kshitij Bhardwaj,et al.  Energy and bandwidth aware mapping of IPs onto regular NoC architectures using Multi-Objective Genetic Algorithms , 2009, 2009 International Symposium on System-on-Chip.

[11]  Magdy A. El-Moursy,et al.  Asynchronous switching for low-power Octagon network-on-chip , 2010, 2010 International Conference on Microelectronics.

[12]  Hamid Sarbazi-Azad,et al.  Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology , 2016, Microprocess. Microsystems.

[13]  Yaseer Arafat Durrani,et al.  High-Level Power Analysis for Intellectual Property-Based Digital Systems , 2014, Circuits Syst. Signal Process..

[14]  Partha Pratim Pande,et al.  A scalable communication-centric SoC interconnect architecture , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[15]  Magdy A. El-Moursy,et al.  Asynchronous switching for low-power networks-on-chip , 2011, Microelectron. J..

[16]  Yang Zhang,et al.  Floorplanning exploration and performance evaluation of a new Network-on-Chip , 2011, 2011 Design, Automation & Test in Europe.

[17]  Luca Benini,et al.  Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Yaseer Arafat Durrani,et al.  Power estimation technique for DSP architectures , 2009, Digit. Signal Process..