Enhanced Detection of Double and Triple Adjacent Errors in Hamming Codes Through Selective Bit Placement

Hamming codes that can correct one error per word are widely used to protect memories or registers from soft errors. As technology scales, radiation particles that create soft errors are more likely to affect more than 1 b when they impact a memory or electronic circuit. This effect is known as a multiple cell upset (MCU), and the registers or memory cells affected by an MCU are physically close. To avoid an MCU from causing more than one error in a given word, interleaving is commonly used in memories. With interleaving, cells that belong to the same logical word are placed apart such that an MCU affects multiple bits but on different words. However, interleaving increases the complexity of the memory device and is not suitable for small memories or content-addressable memories. When interleaving is not used, MCUs can cause multiple errors in a word that may not even be detected by a Hamming code. In this paper, a technique to increase the probability of detecting double and triple adjacent errors when Hamming codes are used is presented. The enhanced detection is achieved by placing the bits of the word such that adjacent errors result in a syndrome that does not match that of any single error. Double and triple adjacent errors are precisely the types of errors that an MCU would likely cause, and therefore, the proposed scheme will be useful to provide error detection for MCUs in memory designs.

[1]  R. Lawrence,et al.  Single Event Effect Induced Multiple-Cell Upsets in a Commercial 90 nm CMOS Digital Technology , 2008, IEEE Transactions on Nuclear Science.

[2]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[3]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[4]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[5]  Sanghyeon Baeg,et al.  SRAM Interleaving Distance Selection With a Soft Error Failure Model , 2009, IEEE Transactions on Nuclear Science.

[6]  P.P. Ankolekar,et al.  Multibit Error-Correction Methods for Latency-Constrained Flash Memory Systems , 2008, IEEE Transactions on Device and Materials Reliability.

[7]  Régis Leveugle Optimized State Assignment of Single Fault Tolerant FSMs Based on SEC Codes , 1993, 30th ACM/IEEE Design Automation Conference.

[8]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..

[9]  Y. Tosaka,et al.  Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's , 2000, IEEE Electron Device Letters.

[10]  André DeHon,et al.  Fault Secure Encoder and Decoder for NanoMemory Applications , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Shi-Jie Wen,et al.  Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[13]  Shu Lin,et al.  Error Control Coding , 2004 .

[14]  Michael Gössel,et al.  New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[15]  Yibing Shi,et al.  A Novel Approach to Improving Burst Errors Correction Capability of Hamming Code , 2007, 2007 International Conference on Communications, Circuits and Systems.

[16]  Nur A. Touba,et al.  Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code , 2007, 25th IEEE VLSI Test Symposium (VTS'07).