Optimization of Low Power 7T SRAM Cell in 45nm Technology

In this paper a low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the performance. A seven transistor (7T) cell at a 45nm feature size in CMOS is proposed to accomplish improvements in stability, power dissipation and performance compared with previous designs for low-power memory operation. By optimizing size and employing the proposed write circuitry scheme, a saving of 45% in power consumption is achieved in memory array operation compared with a conventional 6T SRAM based design. The impact of process variations is investigated in detail, and the CADENCE simulation shows that the 7T SRAM cell has an excellent tolerance to process variations.

[1]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[2]  N. Vallepalli,et al.  SRAM design on 65nm CMOS technology with integrated leakage reduction scheme , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[3]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[4]  Takayasu Sakurai,et al.  90% write power-saving SRAM using sense-amplifying memory cell , 2004 .

[5]  C. Wann,et al.  SRAM cell design for stability methodology , 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

[6]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[7]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[8]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[9]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[10]  Kaushik Roy,et al.  Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors , 2002, ISLPED '02.

[11]  T. Sakurai,et al.  90% write power-saving SRAM using sense-amplifying memory cell , 2004, IEEE Journal of Solid-State Circuits.