A dynamic-threshold SOI device with a J-FET embedded source structure and a merged body-bias-control transistor. II. Circuit simulation

For pt.I see ibid., vol. 47, no.8, p.1587-92 (2000). A primary transistor having an embedded J-FET, or resistor, immediately under the source junction and a small subsidiary body-bias-control transistor enables the construction of a variable-threshold SOI MOSFET with a small area penalty and without any limitation on the power-supply voltage. The subsidiary transistor, synchronized with the gate input signal, injects charges into the body depending on the output-node transient condition and controls the body potential to increase the on-current and decrease the off-current. The embedded J-FET eliminates such floating-body effects as delay hysteresis. The inverter delay time with a 1-pF load capacitance can be shortened to 40% of that of a bulk device under I-V operation, A different embedded J-FET circuit construction under the source enables an NMOS pass gate to be constructed without the output-amplitude degradation caused by the source follower, with a switching speed higher than that of a conventional CMOS pass gate.