A Dual-FPGA Architecture with Rejuvenation for Realtime Applications

This paper focuses on FPGA for realtime applications and proposes a redundant configuration scheme with rejuvenation on a dual-FPGA architecture to handle SEUs. Duplication check is utilized to detect errors within the FPGAs. Rollback and re-computation will be attempted when the error is detected. If the error remains, the rejuvenation will be triggered. The proposed architecture consists of two identical FPGAs. When one FPGA has to undergo a rejuvenation process, the other will be available to operate the system. This ensures the real time computing constraint of an application.