Low-Power High-Speed Analog Multiplier/Divider Based on a New Current Squarer Circuit

In this paper, a CMOS ultra-low-power, high-speed four-quadrant current multiplier/divider circuit is presented. Based on square-difference approach, the proposed circuit is using a new current squarer with MOS transistors operating in weak inversion region. The translinear loops are the basic building blocks in realization of the current-mode two-quadrant squarer and four-quadrant multiplier/divider circuits. The proposed designs have been simulated using HSPICE in 0.18 $$\upmu \hbox {m}$$μm TSMC CMOS (level-49 parameter) process. Post-layout simulation results with 0.8 V power supply show the total power dissipation of 770 nW, the total harmonic distortion of 0.67% (at 100 kHz), the maximum linearity error of 2%, and the − 3 dB bandwidth of 34.1 MHz. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage, and temperature) variations.

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