Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node
暂无分享,去创建一个
[1] A. Asenov,et al. Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations , 2002 .
[2] Tarek Darwish,et al. Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[3] Antonio J. Garcia-Loureiro,et al. Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET , 2014, IEEE Transactions on Electron Devices.
[4] Vivek De,et al. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[5] A. Wang,et al. Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.
[6] Sani R. Nassif,et al. High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.
[7] Mathias Beike,et al. Digital Integrated Circuits A Design Perspective , 2016 .
[8] M. Ieong,et al. Investigation of FinFET Devices for 32nm Technologies and Beyond , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[9] V. Kursun,et al. Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs , 2008, IEEE Transactions on Electron Devices.
[10] Volkan Kursun,et al. FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.
[11] A. Asenov,et al. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .
[12] S. Dasgupta,et al. Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS , 2010, IEEE Transactions on Electron Devices.
[13] Yuan Taur,et al. Fundamentals of Modern VLSI Devices , 1998 .
[14] Samar K. Saha,et al. Modeling Process Variability in Scaled CMOS Technology , 2010, IEEE Design & Test of Computers.
[15] E. Vittoz,et al. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .
[16] James D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.
[17] R.V. Joshi,et al. Leakage power analysis of 25-nm double-gate CMOS devices and circuits , 2005, IEEE Transactions on Electron Devices.
[18] Wolfgang Fichtner,et al. Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.
[19] Kaushik Roy,et al. Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring , 2005, IEEE International Conference on Test, 2005..
[20] Shekhar Y. Borkar,et al. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.
[21] Eric A. Vittoz,et al. Weak Inversion for Ultimate Low-Power Logic , 2004, Low-Power Electronics Design.
[22] Jan M. Rabaey,et al. Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.
[23] Aminul Islam,et al. Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells , 2015, IET Circuits Devices Syst..