Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
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Vivek De | J. Tschanz | S. Narendra | A. Chandrakasan | J. Kao | D. Antoniadis | R. Nair | A. Chandrakasan | J. Tschanz | S. Narendra | R. Nair | V. De | D. Antoniadis | J. Kao
[1] T. Fujita,et al. A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[2] Young,et al. Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic Designs , 1997, 1997 Symposium on VLSI Technology.
[3] Ram Krishnamurthy,et al. A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS , 2002 .
[4] G. Ono,et al. A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[5] Y. Oowaki. A sub-0.1um circuit design with substrate-over-biasing , 1998 .
[6] James D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.
[7] S. Narendra,et al. 1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[8] James T. Kao,et al. Subthreshold leakage control techniques for low power digital circuits , 2001 .
[9] Vivek De,et al. Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).
[10] J.D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[11] 藤田 哲也,et al. A 0.9V 150MHz 10mW 4mm^2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme , 1996 .
[12] Vivek De,et al. Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED '01.