A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors

This paper proposes a high area-efficiency 14-bit column-parallel successive approximation register (SAR) analog-to-digital converter (ADC) for array sensors. A novel hybrid capacitor digital-to-analog converter (CDAC) based on the charge transfer is utilized to increase the area efficiency. It consists of a 9-bit split CDAC and a 5-bit serial CDAC. A foreground digital calibration is employed to compensate for the linearity error caused by the capacitor mismatch and bridge parasitic capacitor. The prototype was designed and fabricated in a 130-nm CMOS technology. Sampling at 200KS/s, the total power consumption is <inline-formula> <tex-math notation="LaTeX">$57~\mu \text{W}$ </tex-math></inline-formula>. With the digital calibration, the proposed ADC achieves the Spurious Free Dynamic Range (SFDR) of 89.14 dB and the Differential Nonlinearity (DNL) of 0.87/-0.99 LSB. The single ADC occupies an active area of <inline-formula> <tex-math notation="LaTeX">$15\times 1450\,\,\mu \text{m}^{2}$ </tex-math></inline-formula> and the area efficiency is only <inline-formula> <tex-math notation="LaTeX">$6.77~\mu \text{m}^{2}$ </tex-math></inline-formula>/code.

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