A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem

In this paper we present a new approach to solving the false path problem. The method is based on our previous work on Timed Boolean Calculus. Given a logic circuit, we first derive timed boolean expressions to model its dynamic behavior. Then, for each term in the expressions, we compute its corresponding sensitizability function, expressed in conjunction normal form; and use an expression in product form to approximate the function. Finally we remove the redundant terms whose sensitizability functions are not satisfiable and determine the maximal delays from the terms remained. Complexity analysis shows that our method identifies false paths and computes delays for sensitizable paths in polynomial time, while experimental results on ISCAS benchmark circuits prove its better efficiency and effectiveness.

[1]  Norman P. Jouppi,et al.  Timing Analysis for nMOS VLSI , 1983, 20th Design Automation Conference Proceedings.

[2]  David Hung-Chang Du,et al.  On the General False Path Problem in Timing Analysis , 1989, 26th ACM/IEEE Design Automation Conference.

[3]  Norman P. Jouppi,et al.  Timing Analysis and Performance Improvement of MOS VLSI Designs , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  David Hung-Chang Du,et al.  A path selection algorithm for timing analysis , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[5]  James E. Smith,et al.  Developments in Logic Network Path Delay Analysis , 1982, DAC 1982.

[6]  David Hung-Chang Du,et al.  Efficient Algorithms for Extracting the K Most Critical Paths in Timing Analysis , 1989, 26th ACM/IEEE Design Automation Conference.

[7]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[8]  James E. Smith,et al.  Developments in Logic Network Path Delay Analysis , 1982, 19th Design Automation Conference.

[9]  Jyuo-Min Shyu,et al.  A new approach to solving false path problem in timing analysis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[10]  Robert K. Brayton,et al.  Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network , 1989, 26th ACM/IEEE Design Automation Conference.

[11]  Hugo De Man,et al.  Static Timing Analysis of Dynamically Sensitizable Paths , 1989, 26th ACM/IEEE Design Automation Conference.

[12]  David Hung-Chang Du,et al.  Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.