论文信息 - Pipelined architecture of reconfigurable specialised processors for a real-time image data pre-processing

Pipelined architecture of reconfigurable specialised processors for a real-time image data pre-processing

This paper presents a multiprocessor unit for fast video image data pre-processing in real time application. The author made a pipelined multiprocessor architecture from specialised hardware processors. This paper presents a reconfigurable specialised hardware processor for this pipelined architecture. The universal reconfigurable processor is implementated in Xilinx FPGA.

K. Wiatr

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