Asynchronous design for programmable digital signal processors
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Teresa H. Y. Meng | David G. Messerschmitt | Robert W. Brodersen | T. Meng | D. Messerschmitt | R. Brodersen
[1] E.A. Lee. Programmable DSP architectures. II , 1989, IEEE ASSP Magazine.
[2] Jack B. Dennis. Modular, asynchronous control structures for a high performance processor , 1970 .
[3] D. V. Bhaskar Rao,et al. Wavefront Array Processor: Language, Architecture, and Applications , 1982, IEEE Transactions on Computers.
[4] L. Heller,et al. Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[5] Alain J. Martin. The Design of a Self-timed Circuit for Distributed Mutual Exclusion , 1983 .
[6] K.C. Saraswat,et al. Effect of scaling of interconnections on the time delay of VLSI circuits , 1982, IEEE Transactions on Electron Devices.
[7] Wesley A. Clark. Macromodular computer systems , 1967, AFIPS '67 (Spring).
[8] T. S. Balraj,et al. Miss Manners: a specialized silicon compiler for synchronizers , 1986 .
[9] Steven M. Burns,et al. The design of an asynchronous microprocessor , 1989, CARN.
[10] Jan L. A. van de Snepscheut,et al. Trace Theory and VLSJ Design , 1985, Lecture Notes in Computer Science.
[11] C. K. Erdelyi. Random logic design utilizing single-ended cascode voltage switch circuits in NMOS , 1985 .
[12] Edsger W. Dijkstra,et al. Guarded commands, nondeterminacy and formal derivation of programs , 1975, Commun. ACM.
[13] Mark A. Franklin,et al. Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks , 1983, IEEE Transactions on Computers.
[14] Teresa H. Y. Meng,et al. A clock-free chip set for high-sampling rate adaptive filters , 1990, J. VLSI Signal Process..
[15] David L. Dill,et al. Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.
[16] Lynn Conway,et al. Introduction to VLSI systems , 1978 .
[17] Peter W. Cook,et al. A 15-ns CMOS 64K RAM , 1986 .
[18] David Misunas,et al. Petri nets and speed independent design , 1973, Commun. ACM.
[19] Charles L. Seitz,et al. Self-Timed VLSI Systems , 1979 .
[20] Edmund M. Clarke,et al. Automatic verification of asynchronous circuits using temporal logic , 1986 .
[21] Erik Brunvand,et al. Translating concurrent programs into delay-insensitive circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[22] Yale N. Patt,et al. Checkpoint Repair for High-Performance Out-of-Order Execution Machines , 1987, IEEE Transactions on Computers.
[23] Robert W. Brodersen,et al. A fully-asynchronous digital signal processor using self-timed circuits , 1990 .
[24] Teresa H. Y. Meng,et al. Automatic synthesis of asynchronous circuits from high-level specifications , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[25] Konstantinos Konstantinides,et al. Design and evaluation of an architecture for a digital signal processor for instrumentation applications , 1990, IEEE Trans. Acoust. Speech Signal Process..
[26] C.H. van Berkel,et al. Compilations of communicating processes into delay-insensitive circuits , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[27] M. Hatamian,et al. Parallel bit-level pipelined VLSI designs for high-speed signal processing , 1987, Proceedings of the IEEE.
[28] Samuel H. Fuller,et al. Cm*: a modular, multi-microprocessor , 1977, AFIPS '77.
[29] C. A. R. Hoare,et al. Communicating sequential processes , 1978, CACM.