Sizing synchronization queues: a case study in higher level synthesis
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In synthesizing a circuit from its description in a concurrent programming language, it is necessary to make decisions about how to implement synchronization constructs such as send and receive statements. The semantic model of these constructs is an infinite length FIFO queue that can handle all send events until they are paired up with corresponding receive events. In this paper, we describe an algorithm to size these synchronization queues while permitting the maximum parallelism between the communicating processes (circuits). It is an example of higher level synthesis in that the user does not include an explicit description of the queue in the specification as is necessary in current high level synthesis systems.
[1] Alice C. Parker,et al. The high-level synthesis of digital systems , 1990, Proc. IEEE.
[2] David C. Ku,et al. HardwareC -- A Language for Hardware Design (Version 2.0) , 1990 .
[3] Carlo H. Séquin,et al. OPERATION/EVENT GRAPHS: A Design Representation for Timing Behavior , 1991 .
[4] Gaetano Borriello,et al. OEsim: a simulator for timing behavior , 1991, 28th ACM/IEEE Design Automation Conference.