A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M*1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test. >

[1]  K. Okada,et al.  Testing System for Redundant Memory , 1982, ITC.

[2]  Younggap You,et al.  A Self-Testing Dynamic RAM Chip , 1985, IEEE Journal of Solid-State Circuits.

[3]  C. Stapper.  Defect density distribution for LSI yield calculations , 1973 .

[4]  K. Fujishima,et al.  A reliable 1-Mbit DRAM with a multi-bit-test mode , 1985, IEEE Journal of Solid-State Circuits.

[5]  S. Inoue,et al.  A 1Mb CMOS DRAM with design-for-test functions , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Gene P. Bosse.  High Speed Redundancy Processor , 1984, ITC.

[7]  Hideto Hidaka,et al.  Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode , 1986, ITC.