Through-Silicon Via Capacitance–Voltage Hysteresis Modeling for 2.5-D and 3-D IC

We propose, for the first time, an explicit semiconductor physics-based through-silicon via (TSV) capacitance–voltage (CV) model. The effect of TSV CV hysteresis is demonstrated in the model, and the TSV capacitance is modeled with respect to dc bias voltage and the dimension of the TSV. The proposed model is verified by comparison to the measurement results. The effect of hysteresis in the model correlates well with the measurement results. This model can be utilized in a circuit level simulation to expand the possible application of the model to, but not limited to, hierarchical power distribution network impedance analysis, RC delay analysis, input–output power consumption analysis, and crosstalk and eye diagram simulation in any 3-D-IC systems using TSVs.

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