High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core
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[1] Giovanni De Micheli,et al. Introduction to Introduction , 2002 .
[2] Anantha Chandrakasan,et al. Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[3] Tsutomu Yoshinaga,et al. Queue Processor Architecture for Novel Queue Queue Processor Architecture for Novel Queue Computing Paradigm Based on Produced Order Scheme Computing Paradigm Based on Produced Order Scheme , 2004 .
[4] Edwin Hsing-Mean Sha,et al. Efficient design exploration based on module utility selection , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] R. Allmon,et al. A 300 MHz 64 b quad-issue CMOS RISC microprocessor , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.
[6] B. Ramakrishna Rau,et al. Automatic architectural synthesis of VLIW and EPIC processors , 1999, Proceedings 12th International Symposium on System Synthesis.
[7] Abderazek Ben Abdallah,et al. Dynamic Fast Issue (DFI) Mechanism for Dynamic Scheduled Processors , 2000 .
[8] T. Yoshinaga,et al. Queue processor architecture for novel queue computing paradigm based on produced order scheme , 2004, Proceedings. Seventh International Conference on High Performance Computing and Grid in Asia Pacific Region, 2004..
[9] Benjamin Bishop,et al. The design of a register renaming unit , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.
[10] Tsutomu Yoshinaga,et al. Parallel Queue Processor Architecture Based on Produced Order Computation Model , 2005, The Journal of Supercomputing.
[11] Edwin Hsing-Mean Sha,et al. Hardware/Software co-design with the HMS framework , 1996, J. VLSI Signal Process..
[12] Anantha Chandrakasan,et al. Quantifying and enhancing power awareness of VLSI systems , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[13] Norio Nakagawa,et al. Functional verification of the superscalar SH-4 microprocessor , 1997, Proceedings IEEE COMPCON 97. Digest of Papers.
[14] Vaughn Betz,et al. The stratixπ routing and logic architecture , 2003, FPGA '03.
[15] Robert A. Walker,et al. A solution methodology for exact design space exploration in a three-dimensional design space , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[16] Tsutomu Yoshinaga,et al. A Reduced Bit - Width Instruction Set Architecture for FQM Execution in Hybrid Processor Architecture(FaRM - rq) , 2003 .
[17] David Harel,et al. Statecharts: A Visual Formalism for Complex Systems , 1987, Sci. Comput. Program..
[18] Tsutomu Yoshinaga,et al. Proposal and Design of a Parallel Queue Processor Architecture (PQP) , 2002, IASTED PDCS.
[19] Giovanni De Micheli,et al. Readings in hardware / software co-design , 2001 .