New Assessment Methodology Based on Energy–Delay–Yield Cooptimization for Nanoscale CMOS Technology

A new technology assessment methodology is proposed to simultaneously evaluate circuit-level energy, delay, and yield under realistic device operation theme through Monte Carlo analysis. Given any yield constraints, this new methodology can maximize the circuit energy efficiency without overdesign. It provides a method to quantify the tradeoff between energy-delay (ED) and yield. The proposed method is proved to be efficient especially for low power circuit applications compared with ED-only approach. Taking 14-nm FinFET design, for example, the impacts of major variation sources are analyzed for different circuit applications, showing a different trend from the ED-only approach. In addition, the methodology is also extended to include the impacts of reliability issues. A desired design strategy is found to balance the design merits and circuit reliability. The proposed methodology is helpful for technology assessment and early stage circuit design and planning.

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