Design of Area-Efficient FIR Filter Based on ALU Architecture

A novel ALU architecture-based FIR filter was designed,in which convolution operation was realized with memory and counters.With increasing order of FIR filter,logic gate counts remain unchanged,and memory capacity increases linearly,rather than exponentially as in conventional distributed arithmetic(DA) architecture.Consequently,equivalent logic gate counts decreased dramatically in ALU-based FIR filter.FPGA synthesis results show that,when the order of filter is greater than 64 taps,the proposed circuit has far less equivalent logic gate counts than the conventional DA approach.