A detailed power model for field-programmable gate arrays

Power has become a critical issue for field-programmable gate array (FPGA) vendors. Understanding the power dissipation within FPGAs is the first step in developing power-efficient architectures and computer-aided design (CAD) tools for FPGAs. This article describes a detailed and flexible power model which has been integrated in the widely used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.

[1]  Farid N. Najm Low-pass filter for computing the transition density in digital circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Jonathan Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[3]  Farid N. Najm,et al.  Power estimation techniques for integrated circuits , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[4]  J. Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2000, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Sarma Vrudhula,et al.  A new short circuit power model for complex CMOS gates , 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

[6]  Farid N. Najm Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits , 1995, 32nd Design Automation Conference.

[7]  Chak-Kuen Wong,et al.  Universal switch modules for FPGA design , 1996, TODE.

[8]  Per Larsson-Edefors,et al.  Interconnect-driven short-circuit power modeling , 2001, Proceedings Euromicro Symposium on Digital Systems Design.

[9]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Farid N. Najm Power estimation techniques for integrated circuits , 1995, ICCAD.

[12]  George Varghese,et al.  The design of a low energy FPGA , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[13]  Julien Lamoureux,et al.  On the Interaction Between Power-Aware FPGA CAD Algorithms , 2003, ICCAD 2003.

[14]  Steven J. E. Wilton,et al.  A New Switch Block for Segmented FPGAs , 1999, FPL.

[15]  Jan-Min Hwang,et al.  A re-engineering approach to low power FPGA design using SPFD , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[16]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[17]  Jason Cong,et al.  Architecture evaluation for power-efficient FPGAs , 2003, FPGA '03.

[18]  Vaughn Betz,et al.  VPR and T-VPack User''s Manual , 2000 .

[19]  Kaushik Roy,et al.  Intrinsic leakage in low power deep submicron CMOS ICs , 1997, Proceedings International Test Conference 1997.

[20]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[21]  Robert G. Meyer,et al.  An engineering model for short-channel MOS devices , 1988 .

[22]  C. P. Ravikumar,et al.  Leakage power estimation for deep submicron circuits in an ASIC design environment , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[23]  TingTing Hwang,et al.  A re-engineering approach to low power FPGA design using SPFD , 1998, DAC.

[24]  Shin Min Kang,et al.  CMOS Digital Integrated Cir-cuits: Analysis and Design , 2002 .

[25]  Gary K. Yeap,et al.  Practical Low Power Digital VLSI Design , 1997 .

[26]  Chi-Ying Tsui,et al.  Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs , 1994, 31st Design Automation Conference.

[27]  Li Shang,et al.  Dynamic power consumption in Virtex™-II FPGA family , 2002, FPGA '02.

[28]  Jan M. Rabaey,et al.  Reconfigurable platform design for wireless protocol processors , 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

[29]  Steven J. E. Wilton,et al.  On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques , 2002, FPGA '02.