Diagnostic Fault Simulation of Sequential Circuits

In this work we describe a diagnostic fault simulator for sequential circuits which evaluates the effectiveness of a given test set in distinguishing between faults. Diagnostic fault simulation is performed on several ISCAS89 sequential benchmark circuits using two diferent deterministic test sets for each circuit. Several diagnostic measures are reported, including the diagnostic resolution, the diagnostic power, and the sizes of the indistinguishable fault classes. In addition, lists of indistinguishable faults are generated. Use of the diagnostic fault simulator to diagnose faults, given the output responses of failing devices, is also described.

[1]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[2]  Paolo Prinetto,et al.  Diagnosis oriented test pattern generation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[3]  Resve A. Saleh,et al.  Exact evaluation of diagnostic test resolution , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[4]  S. Davidson,et al.  Sequential Circuit Test Generator (STG) benchmark results , 1989, IEEE International Symposium on Circuits and Systems,.

[5]  John A. Waicukauski,et al.  Fault Diagnosis in an LSSD Environment , 1981, ITC.

[6]  Sundaram Seshu,et al.  On an Improved Diagnosis Program , 1965, IEEE Trans. Electron. Comput..

[7]  Elizabeth M. Rudnick,et al.  Methods for reducing events in sequential circuit fault simulation , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[8]  Janak Himatlal Patel.  Improving the throughput of pipelines with delays and buffers , 1976 .

[9]  Wu-Tung Cheng,et al.  Differential Fault Simulation - A Fast Method Using Minimal Memory , 1989, 26th ACM/IEEE Design Automation Conference.

[10]  Janak H. Patel,et al.  PROOFS: a fast, memory-efficient sequential circuit fault simulator , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  W. Kent Fuchs,et al.  TWO-STAGE FAULT LOCATION , 1991, 1991, Proceedings. International Test Conference.

[12]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[13]  J. A. Waicukauski.  Diagnosis of BIST Failures by PPSFP simulation , 1987 .

[14]  Paul H. Bardell,et al.  Production experience with built-in self-test in the IBM ES/9000 system , 1991, 1991, Proceedings. International Test Conference.