We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms/spl minus/edge-triggered and level-sensitive/spl minus/for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.<<ETX>>
[1]
Alice C. Parker,et al.
Data path tradeoffs using MABAL
,
1991,
DAC '90.
[2]
Robert K. Brayton,et al.
MIS: A Multiple-Level Logic Optimization System
,
1987,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3]
Wayne H. Wolf,et al.
The Princeton University behavioral synthesis system
,
1992,
[1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[4]
A. Jerraya,et al.
DLS: A scheduling algorithm for high-level synthesis in VHDL
,
1993,
1993 European Conference on Design Automation with the European Event in ASIC Design.
[5]
Raul Camposano,et al.
Path-based scheduling for synthesis
,
1991,
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6]
R. Composano,et al.
Path-based scheduling for synthesis
,
1990,
Twenty-Third Annual Hawaii International Conference on System Sciences.