Comprehensive Modeling Methodologies for NoC Router Estimation
暂无分享,去创建一个
[1] Raphael T. Haftka,et al. Surrogate-based Analysis and Optimization , 2005 .
[2] Andrew B. Kahng,et al. Improved on-chip router analytical power and area modeling , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[3] Alexander J. Smola,et al. Support Vector Method for Function Approximation, Regression Estimation and Signal Processing , 1996, NIPS.
[4] Bill Lin,et al. Comprehensive Modeling Methodologies for NoC Router Estimation Andrew B. Kahng Bill Lin Siddhartha Nath , 2012 .
[5] Sri Parameswaran,et al. NoCEE: energy macro-model extraction methodology for network on chip routers , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[6] Georges G. E. Gielen,et al. Performance modeling of analog integrated circuits using least-squares support vector machines , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[7] Jih-Sheng Shen,et al. A low-power crossroad switch architecture and its core placement for network-on-chip , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[8] Vittorio Zaccaria,et al. OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Andrew B. Kahng,et al. Explicit modeling of control and data for improved NoC router estimation , 2012, DAC Design Automation Conference 2012.
[10] Timothy W. Simpson,et al. Metamodels for Computer-based Engineering Design: Survey and recommendations , 2001, Engineering with Computers.
[11] Frank Liu,et al. A General Framework for Spatial Correlation Modeling in VLSI Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[12] Andrew B. Kahng,et al. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[13] A. A. Ilumoka. Efficient prediction of crosstalk in VLSI interconnections using neural networks , 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).
[14] Jia Xinzhang,et al. Analysis on the effect of regression and correlation models on the accuracy of Kriging model for IC , 2009, 2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).
[15] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[16] Orion: a power-performance simulator for interconnection networks , 2002, MICRO 35.
[17] Andrew B. Kahng,et al. Accurate Machine-Learning-Based On-Chip Router Modeling , 2010, IEEE Embedded Systems Letters.
[18] Hans C. van Houwelingen,et al. The Elements of Statistical Learning, Data Mining, Inference, and Prediction. Trevor Hastie, Robert Tibshirani and Jerome Friedman, Springer, New York, 2001. No. of pages: xvi+533. ISBN 0‐387‐95284‐5 , 2004 .
[19] Niraj K. Jha,et al. GARNET: A detailed on-chip network model inside a full-system simulator , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.
[20] Li-Shiuan Peh,et al. Flow control and micro-architectural mechanisms for extending the performance of interconnection networks , 2001 .
[21] M. B. Yelten,et al. Demystifying Surrogate Modeling for Circuits and Systems , 2012, IEEE Circuits and Systems Magazine.
[22] Bernhard Schölkopf,et al. A tutorial on support vector regression , 2004, Stat. Comput..
[23] Ashutosh Kumar Singh,et al. The Elements of Statistical Learning: Data Mining, Inference, and Prediction , 2010 .
[24] E. S. Siah,et al. Fast parameter optimization of large-scale electromagnetic objects using DIRECT with Kriging metamodeling , 2004, IEEE Transactions on Microwave Theory and Techniques.
[25] David M. Brooks,et al. Accurate and efficient regression modeling for microarchitectural performance and power prediction , 2006, ASPLOS XII.
[26] Sonja Kuhnt,et al. Design and analysis of computer experiments , 2010 .
[27] J. Freidman,et al. Multivariate adaptive regression splines , 1991 .
[28] Miss A.O. Penney. (b) , 1974, The New Yale Book of Quotations.
[29] Søren Nymand Lophaven,et al. Aspects of the Matlab toolbox DACE , 2002 .
[30] Luca Benini,et al. Area and Power Modeling for Networks-on-Chip with Layout Awareness , 2007, VLSI Design.
[31] Axel Jantsch,et al. A High Level Power Model for the Nostrum NoC , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).
[32] Sudhakar Yalamanchili,et al. Power constrained design of multiprocessor interconnection networks , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.
[33] Gianluca Palermo,et al. PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures , 2004, PATMOS.
[34] Luca Benini,et al. Analysis of power consumption on switch fabrics in network routers , 2002, DAC '02.
[35] Sally A. McKee,et al. Efficiently exploring architectural design spaces via predictive modeling , 2006, ASPLOS XII.
[36] T. Simpson,et al. Comparative studies of metamodeling techniques under multiple modeling criteria , 2000 .
[37] R. Brereton,et al. Support vector machines for classification and regression. , 2010, The Analyst.
[38] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[39] Simon W. Moore,et al. The design and implementation of a low-latency on-chip network , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[40] S. Nassif,et al. Accurate Spatial Estimation and Decomposition Techniques for Variability Characterization , 2010, IEEE Transactions on Semiconductor Manufacturing.
[41] Karam S. Chatha,et al. A power and performance model for network-on-chip architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[42] Seung Eun Lee,et al. A high level power model for Network-on-Chip (NoC) router , 2009, Comput. Electr. Eng..
[43] Vittorio Zaccaria,et al. A correlation-based design space exploration methodology for multi-processor systems-on-chip , 2010, Design Automation Conference.
[44] Fernando Gehm Moraes,et al. NoC Power Estimation at the RTL Abstraction Level , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.
[45] Rob A. Rutenbar,et al. Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.