VLSI oriented fast motion estimation algorithm based on macroblock and motion feature analysis

The latest H.264/AVC standard can provide us superior coding performance. However, the new technique also brings about complexity problem, especially in motion estimation (ME) part. In hardware, the pipeline stage division of H.264 based ME engine degrades many software oriented complexity reduction schemes. In our paper, we propose one VLSI friendly fast ME algorithm. Firstly, pixel difference based adaptive subsampling achieves complexity reduction for homogeneous macroblock (MB). Secondly, a multiple reference frame elimination scheme is introduced to early terminate ME process for static MB. Thirdly, based on the motion feature analysis, the search range is adjusted to remove redundant search points. Experimental results show that, compared with hardware friendly full search algorithm, our proposed algorithm can reduce 71.09% to 95.26%ME time with negligible video quality degradation. Moreover, our fast algorithm can be combined with existing fast motion estimation algorithms such as UMHexagon search for further reduction in complexity and it is friendly to hardware implementation.

[1]  Zhenyu Liu,et al.  Adaptive Edge Detection Pre-Process Multiple Reference Frames Motion Estimation in H.264/AVC , 2007, 2007 International Conference on Communications, Circuits and Systems.

[2]  Ming-Chieh Chi,et al.  Efficient multi-frame motion estimation algorithms for MPEG-4 AVC/JVT/H.264 , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[3]  Zhenyu Liu,et al.  Hardware friendly background analysis based complexity reduction in H.264/AVC multiple reference frames motion estimation , 2007, 2007 International Symposium on Intelligent Signal Processing and Communication Systems.

[4]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..

[5]  Liang-Gee Chen,et al.  Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC , 2006, IEEE Transactions on Circuits and Systems for Video Technology.

[6]  Liang-Gee Chen,et al.  Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264 , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[7]  Liang-Gee Chen,et al.  Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder , 2006, IEEE Transactions on Circuits and Systems for Video Technology.

[8]  Thomas Wedi,et al.  Motion- and aliasing-compensated prediction for hybrid video coding , 2003, IEEE Trans. Circuits Syst. Video Technol..

[9]  Gary J. Sullivan,et al.  Rate-constrained coder control and comparison of video coding standards , 2003, IEEE Trans. Circuits Syst. Video Technol..

[10]  G. Bjontegaard,et al.  Calculation of Average PSNR Differences between RD-curves , 2001 .