Gallager B LDPC Decoder with Transient and permanent errors
暂无分享,去创建一个
[1] Ronen Shaltiel,et al. Invertible Zero-Error Dispersers and Defective Memory with Stuck-At Errors , 2012, APPROX-RANDOM.
[2] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[3] Lav R. Varshney,et al. Performance of LDPC Codes Under Faulty Iterative Decoding , 2008, IEEE Transactions on Information Theory.
[4] Christoph Roth,et al. Data mapping for unreliable memories , 2012, 2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton).
[5] Ashish Jagmohan,et al. Algorithms for memories with stuck cells , 2010, 2010 IEEE International Symposium on Information Theory.
[6] Lara Dolecek,et al. Gallager B Decoder on Noisy Hardware , 2013, IEEE Transactions on Communications.
[7] H. Vincent Poor,et al. Density evolution for asymmetric memoryless channels , 2005, IEEE Transactions on Information Theory.
[8] Shashi Kiran Chilappagari,et al. Analysis of One Step Majority Logic Decoders Constructed From Faulty Gates , 2006, 2006 IEEE International Symposium on Information Theory.
[9] Chris Winstead,et al. A Probabilistic LDPC-Coded Fault Compensation Technique for Reliable Nanoscale Computing , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[10] Frans P. M. Beenker,et al. A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] B. Johnson,et al. Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology , 2004 .
[12] Lara Dolecek,et al. Gallager B LDPC Decoder with Transient and Permanent Errors , 2013, IEEE Transactions on Communications.
[13] Bane V. Vasic,et al. Analytical Performance of One-Step Majority Logic Decoding of Regular LDPC Codes , 2007, 2007 IEEE International Symposium on Information Theory.
[14] D. Spielman,et al. Expander codes , 1996 .
[15] Shashi Kiran Chilappagari,et al. An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[16] David J. C. MacKay,et al. Encyclopedia of Sparse Graph Codes , 1999 .
[17] Naresh R. Shanbhag,et al. Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[18] Shashi Kiran Chilappagari,et al. Instanton-based techniques for analysis and reduction of error floors of LDPC codes , 2009, IEEE Journal on Selected Areas in Communications.
[19] Rüdiger L. Urbanke,et al. The capacity of low-density parity-check codes under message-passing decoding , 2001, IEEE Trans. Inf. Theory.
[20] Farshad Lahouti,et al. Performance Analysis of Noisy Message-Passing Decoding of Low-Density Parity-Check Codes , 2010 .
[21] Chris Heegard. Partitioned linear block codes for computer memory with 'stuck-at' defects , 1983, IEEE Trans. Inf. Theory.
[22] Subhasish Mitra,et al. Overcoming Early-Life Failure and Aging for Robust Systems , 2009, IEEE Design & Test of Computers.
[23] Tetsunao Matsuta,et al. 国際会議開催報告:2013 IEEE International Symposium on Information Theory , 2013 .
[24] François Leduc-Primeau,et al. Faulty Gallager-B decoding with optimal message repetition , 2012, 2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton).
[25] Wei Yu,et al. Complexity-optimized low-density parity-check codes for gallager decoding algorithm B , 2005, Proceedings. International Symposium on Information Theory, 2005. ISIT 2005..
[26] Christoforos N. Hadjicostis,et al. Coding approaches to fault tolerance in linear dynamic systems , 2005, IEEE Transactions on Information Theory.
[27] Michael G. Taylor. Reliable information storage in memories designed from unreliable components , 1968 .
[28] Shashi Kiran Chilappagari,et al. On Trapping Sets and Guaranteed Error Correction Capability of LDPC Codes and GLDPC Codes , 2008, IEEE Transactions on Information Theory.
[29] Lara Dolecek,et al. Optimal Design of a Gallager B Noisy Decoder for Irregular LDPC Codes , 2012, IEEE Communications Letters.
[30] David Declercq,et al. Min-Sum-based decoders running on noisy hardware , 2013, 2013 IEEE Global Communications Conference (GLOBECOM).
[31] Ad J. van de Goor,et al. Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..
[32] B. Vasic,et al. Fault Tolerant Memories Based on Expander Graphs , 2007, 2007 IEEE Information Theory Workshop.
[33] Christophe Jégo,et al. An LDPC decoding method for fault-tolerant digital logic , 2012, 2012 IEEE International Symposium on Circuits and Systems.
[34] Yervant Zorian,et al. Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[35] J. von Neumann,et al. Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .
[36] Shashi Kiran Chilappagari,et al. On the Construction of Structured LDPC Codes Free of Small Trapping Sets , 2012, IEEE Transactions on Information Theory.
[37] J.A. Abraham,et al. Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures , 1986, Proceedings of the IEEE.