An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller
暂无分享,去创建一个
T. Tanaka | Y. Ohji | M. Ushiyama | K. Shohji | T. Wada | K. Shimohigashi | T. Nishimoto | T. Hagiwara | K. Seki | H. Kume | S. Saeki | T. Adachi | N. Miyamoto | K. Komori | K. Izawa | Y. Kubota | N. Ogawa | T. Tanaka | K. Shimohigashi | Y. Ohji | T. Nishimoto | H. Kume | K. Seki | N. Miyamoto | T. Adachi | M. Ushiyama | T. Hagiwara | S. Saeki | K. Komori | T. Wada | K. Izawa | Y. Kubota | K. Shohji | N. Ogawa
[1] Alan Baker,et al. An in-system reprogrammable 32 K*8 CMOS flash memory , 1988 .
[2] G. Smarandoiu,et al. A 128 K flash EEPROM using double-polysilicon technology , 1987 .
[3] R.-A. Cernea,et al. A 1 Mb flash EEPROM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.
[4] B. Vajdic,et al. A 90-ns one-million erase/program cycle 1-Mbit flash memory , 1989 .