A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands

This brief delineates the design and realization of a 10-GS/s 4-bit digital-to-analog converter (DAC) for the cognitive ultrawideband (CUWB), an emerging solution for low interference and efficient spectrum utilization in communication networks. The DAC serves as the data converter for the adaptive waveform transmitter therein, largely to reduce its power dissipation and hardware complexity. For reasons of low power dissipation and low-cost CUWB application, the resolution of the DAC is 4 bits, its realization is in standard 65-nm CMOS, and the architecture is a single core. The binary current-steering DAC includes critical building blocks such as current sources and a novel deglitcher circuit. The current sources are designed for small area with high linearity based on our derived relationship between current-source output resistance and linearity parameters [integral nonlinearity (INL) and spurious-free dynamic range (SFDR)]. The deglitcher design includes high-speed source followers as high-speed low voltage swing buffers to improve the linearity by decreasing the output glitch energy. The DAC embodies an in situ hardware efficient (small integrated-circuit area and reduced input/output pinout) tester that generates 4 × 10-Gb/s test-data pattern to facilitate functional verification. The designed DAC achieves ≤ 0.16-least significant bit INL/differential nonlinearity and > 23-dBc SFDR over the Nyquist bandwidth up to 4.53 GHz, and features the most competitive figures-of-merit of all similar DACs reported to date.

[1]  Luís Bica Oliveira,et al.  A Pulse Generator for UWB-IR Based on a Relaxation Oscillator , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Honggang Zhang,et al.  Multiple signal waveforms adaptation in cognitive ultra-wideband radio evolution , 2006, IEEE Journal on Selected Areas in Communications.

[3]  H. Gustat,et al.  A 30 GS/s 4-Bit Binary Weighted DAC in SiGe BiCMOS Technology , 2007, 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[4]  M. Steyaert,et al.  A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC , 2007, IEEE Journal of Solid-State Circuits.

[5]  Tian Xia,et al.  A High-Performance Low-Ringing Ultrawideband Monocycle Pulse Generator , 2012, IEEE Transactions on Instrumentation and Measurement.

[6]  H. Nosaka,et al.  A 60-GS/s 6-Bit DAC in 0.5-µm InP HBT Technology for Optical Communications Systems , 2011, 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

[7]  Arthur H. M. van Roermund,et al.  A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Michiel Steyaert,et al.  A 130 nm CMOS 6-bit full nyquist 3GS/s DAC , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[9]  W. Schofield,et al.  A 16b 400MS/s DAC with <-80dBc IMD to 300MHz and <-160dBm/Hz noise power spectral density , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[10]  Marinette Besson,et al.  A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Hae-Seung Lee,et al.  Output impedance requirements for DACs , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[12]  W. Sansen,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[13]  Joseph Sylvester Chang,et al.  Design of a 5 GS/s fully-digital digital-to-analog converter , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).