Test time reduction through minimum execution of tester-hardware setting instructions

The introduction of low-priced test systems and the reduction of the test time are necessary in order to decrease the testing costs that are included in the cost of manufacturing VLSI. However, coupled with the miniaturization of the fabrication process, the test time tends to become considerably longer for multifunctional and complex VLSI with high integration. In this paper, we present a new method enabling the automatic reduction of the test time. This method consists of shortening the test time by installing virtual tester hardware on the tester CPU memory in order to delete duplicate tester hardware setting instructions. The efficiency of this method is proven by experiments showing that a test time reduction of 5/spl sim/25% could be obtained.