Comprehensive models for the investigation of on-chip switching noise generation and coupling

A comprehensive modeling methodology is presented for the investigation of on-chip noise generation and coupling due to power switching. The methodology utilizes a comprehensive electromagnetic model for the on-chip portion of the power grid. Thus, the tedious and error-prone extraction of a distributed RLC model for the power grid is avoided and the generated model allows for power grid induced broadband and distributed noise coupling to be taken into account in the transient simulation. The electromagnetic model for the power grid is complemented by a distributed RC model for the semiconductor substrate and RLCG models for the interconnects. Thus, a comprehensive model results for the quantification of on-chip interconnect and power grid noise effects during switching. Transient simulations using this model are carried out using a hybrid time-domain integration scheme which combines a SPICE-like engine for the analysis of all RLCG netlists and the nonlinear drivers incorporated in the model with a numerical integration algorithm for the discrete electromagnetic model for the power grid

[1]  Myoung Joon Choi,et al.  A quasi three-dimensional distributed electromagnetic model for complex power distribution networks , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[2]  Kishore Singhal,et al.  Computer Methods for Circuit Analysis and Design , 1983 .

[3]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[4]  Allen Taflove,et al.  Computational Electrodynamics the Finite-Difference Time-Domain Method , 1995 .

[5]  Hugo De Man,et al.  High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects , 2004, Proceedings. 41st Design Automation Conference, 2004..

[6]  G. Manetas,et al.  Methodology for expedient computation of semiconductor substrate noise coupling , 2004, Electrical Performance of Electronic Packaging - 2004.

[7]  Xavier Aragones,et al.  Experimental comparison of substrate noise coupling using different wafer types , 1999 .

[8]  A.C. Cangellaris,et al.  Distributed on-chip power grid modeling: an electromagnetic alternative to RLC extraction-based models , 2003, Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).

[9]  Myoung Joon Choi,et al.  A quasi three-dimensional distributed electromagnetic model for complex power distribution networks , 2002 .

[10]  Shoichi Masui,et al.  Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits , 1993 .

[11]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[12]  A.C. Cangellaris,et al.  Comprehensive Model for On-Chip Power Grid Transient Analysis and Power Grid-Induced Noise Prediction , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..