An Algorithm Based Concurrent Error Detection Scheme for AES

With the wide-spread practical applications of AES, not only high performance, but also strong reliability is desirable to all the cryptosystem. In this paper, a lightweight concurrent AES error detection scheme which is based on the algorithm based fault tolerant (ABFT) technique is proposed. Two versions of scheme are presented to satisfy different application requirements. The first general version scheme can detect single error for the whole AES process with high efficiency. Another run-time version scheme is used to immediately end the error round with no time delay and no computation wasted on the rest rounds for propagating errors. Utilizing the ready-made arithmetic units in AES, single error can be detected by the sender and prevent the misdirected information from sending out. The results of the hardware FPGA implementation and simulation show that the proposed scheme can be integrated both on software and hardware without making many changes to the original AES implementation.

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