POWER8 design methodology innovations for improving productivity and reducing power

The design complexity of modern high performance processors calls for innovative design methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets. This paper describes new design approaches employed by the POWER8 processor design team to address complexity and power consumption challenges. Improvements in productivity are attained by leveraging a new and more synthesis-centric design methodology. New optimization strategies for synthesized macros allow power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor. Overall, POWER8 delivers a 2.5x increase in per-socket performance over its predecessor, POWER7+, while maintaining the same power dissipation.

[1]  Haifeng Qian,et al.  Design methodology for the IBM POWER7 microprocessor , 2011, IBM J. Res. Dev..

[2]  E. Fluhr,et al.  Design and Implementation of the POWER6 Microprocessor , 2008, IEEE Journal of Solid-State Circuits.

[3]  Andrew R. Conn,et al.  Optimization of custom MOS circuits by transistor sizing , 1996, Proceedings of International Conference on Computer Aided Design.

[4]  Matthew M. Ziegler,et al.  Network flow based datapath bit slicing , 2013, ISPD '13.

[5]  Matthew M. Ziegler,et al.  Power reduction by aggressive synthesis design space exploration , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[6]  William J. Dally,et al.  The role of custom design in ASIC chips , 2000, Proceedings 37th Design Automation Conference.

[7]  Matthew M. Ziegler,et al.  LatchPlanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Louise Trevillyan,et al.  An integrated environment for technology closure of deep-submicron IC designs , 2004, IEEE Design & Test of Computers.

[9]  H. Murakami,et al.  A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit , 2007, 2007 IEEE Symposium on VLSI Circuits.

[10]  Sameh W. Asaad,et al.  Design methodology for semi custom processor cores , 2004, GLSVLSI '04.

[11]  Victor V. Zyuban,et al.  IBM POWER7+ design for higher frequency at fixed power , 2013, IBM J. Res. Dev..

[12]  Christopher Gonzalez,et al.  5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[13]  S. Narasimha,et al.  22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL , 2012, 2012 International Electron Devices Meeting.

[14]  Matthew M. Ziegler,et al.  The opportunity cost of low power design: a case study in circuit tuning , 2009, ISLPED.