Logic and physical synthesis techniques for engineering change orders (ecos)

Recent decades have seen rapid advancement in the speed, dimensions and complexity of VLSI integrated circuits. This growth has been enabled by powerful and easy to use electronic design automation (EDA) tools. EDA tools have allowed designers to meet chip design cycles more efficiently. Academic and industrial research for various stages of design flow such as synthesis, placement, routing, and verification has resulted in EDA tools becoming mature, robust and comprehensive. As designs become more complex and design cycles shrink, they increasingly undergo small scale changes that are typically made late in the design cycles—either in order to correct errors found or else to meet late stage specification changes. Such changes are referred to as Engineering Change Orders (ECOs). With the probability of ECOs increasing with each technology node, they not only increase Non-Recurring Engineering (NRE) and mask set costs, but also result in lost market opportunities for manufacturers due to whole design re-spin delays. To avoid this, previous designs must be modified incrementally rather than undergoing a complete re-spin. However, the current industrial EDA tool suites do not handle ECOs in a systematic manner. The ECO algorithms and techniques in such tool suites lag behind in scale, sophistication and complexity compared to their non-ECO counterparts. More often, this has resulted in designers carrying out ECOs manually often at increased design time, costs and inferior performance of chips. Hence, it is essential to have a flow that can operate in an incremental fashion for various stages of design cycle. In this dissertation, we focus on developing various logic and physical synthesis techniques for ECOs. The goal is to provide a set of algorithms and techniques specifically created to tackle incremental changes during various stages of design cycle in an efficient manner. We first propose DeltaSyn, a tool and methodology for identifying and generating a highly optimized logic difference between a modified high-level specification and an implemented design. DeltaSyn allows a designer to locate similar logic in the original design which can be reused to realize the modified specification through several analysis techniques applied in sequence. We then propose ECO-Map, a framework that finds a physical realization of the given logic difference using only the placed recycled or spare cells on a die such that the transistor masks remain intact and only the less expensive metal masks are affected. We then present ECO-Route, a routing methodology aimed at reducing the cost and effort associated with mask changes. This is accomplished by minimizing the number of affected metal and via layers during technology remapping and detailed routing phases respectively.