The possibility of PMD compensation by using LDPC-coded turbo equalization is demonstrated experimentally for NRZ systems operating at 10-Gb/s. Significant BER performance improvement over the optimum threshold receiver is obtained. Introduction The performance of wavelength division multiplexed (WDM) systems operating at high-speeds are affected by fiber nonlinearities and polarization-mode dispersion (PMD) [1-3]. Contrary to the chromatic dispersion, the PMD is time variant and stochastic in nature, making the PMD compensation more challenging to implement. Recently, several electrical and optical PMD compensators have been proposed [1,3,6], including Viterbi equalizer [1], Bahl, Cocke, Jelinek and Raviv (BCJR) equalizer [2-4], and turbo equalizer [3-6]. In this paper we demonstrate experimentally that lowdensity parity-check (LDPC)-coded turbo equalizer is an excellent PMD compensator candidate capable of compensating for the differential group delay (DGD) in excess of 125ps with 2.5 dB penalty from undistorted case (0 ps of DGD) at bit-error rate (BER) of 10. The considered scheme is composed of two components: (i) BCJR equalizer [2-4], and (ii) lowdensity parity-check (LDPC) decoder. BCJR equalizer is used partially to cancel the intersymbol interference (ISI) introduced by PMD, reduce the BER down to the decoder BER threshold, and to provide the loglikelihood ratios (LLRs) passed to the LDPC decoder based on an efficient implementation of sum-product algorithm. A special class of structured LDPC codes, based on combinatorial objects known as balanced incomplete block designs (BIBDs) [7], is employed to enable the iteration of extrinsic information between BCJR equalizer and LDPC decoder (also known as turbo equalizer), and at the same time to facilitate the implementation at high-speeds. The extrinsic information transfer (EXIT) chart analysis [8] is used to verify the suitability of designed LDPC codes for turbo equalization of PMD. The simulation results reported in [6] indicate that proposed scheme can be used to compensate for DGD up to 300 ps for reasonable complexity of BCJR equalizer. The experimental results in this paper are reported for DGDs up to 125 ps for a non-return to zero (NRZ) transmission system operating at 10-Gb/s. Experimental setup and PMD compensator The experimental setup for NRZ transmission is given in Fig. 1. As mentioned in Introduction (see also Fig. 1), the LDPC-coded turbo equalizer is composed of two parts: (i) BCJR equalizer, and (ii) LDPC decoder. The BCJR equalizer operates on a discrete dynamical trellis description of the optical channel, as explained in our previous article [2]. Essentially, the optical channel is described as an ISI channel with memory 2m+1, where m previous and m next bits influence the observed bit. The trellis from [2] is uniquely determined by the set of triples: previous state, channel output, next state. The state s=(xj-m,xjm+1,..,xj,xj+1,...,xj+m) is determined by the sequence of 2m+1 input bits xi∈X={0,1} that influence the observed bit xj. For the complete description of the trellis, the transition probability density functions (PDFs) p(yj|s), are determined from histograms collected experimentally (yj represent the sample at the input of the BCJR equalizer that corresponds to the transmitted bit xj). As an illustration, Fig. 2(a) shows the conditional PDFs of the received sample y given a state s=‘11011’ or ‘00100’ for different DGD values. As DGD increases, the PDF mean for state s=‘11011’ shifts to the right, PDF curve becomes wider, and BER performance degrades. The BCJR equalizer operates on trellis from [2], partially cancels the ISI due to PMD, and reduces the BER. A significant advantage of using the BCJR equalizer, compared to Viterbi equalizer, is that in addition to detected bits it also provides the LLRs (bit reliabilities, i.e. soft decisions) required for LDPC soft decoding. The full advantage of iterative decoding can be achieved only if soft bit reliabilities are available for decoding. The LDPC decoder operates by processing BCJR LLRs using sum-product algorithm. The extrinsic LLRs of the LDPC decoder, determined as difference between LDPC decoder output and input LLRs, are forwarded back to the BCJR equalizer. We refer to this step as an outer iteration, to differentiate it from iterations within the sum-product algorithm, which are referred to as inner iterations. Different turbo equalization schemes (e.g., [3,5]) require the use of interleavers. The proposed turbo equalization scheme is based on LDPC codes, and as such does not require the use interleavers. This reduces the processing delay and facilitates the implementation at high-speed. The LDPC codes employed in this paper are girth-8 LDPC codes designed using the concept of BIBDs [7]. In Fig. 2(b) the BER performance of proposed LDPC code (for 30 iterations in sumproduct decoding algorithm) is compared against RS, concatenated RS, and turbo-product codes (on an AWGN channel). The rate R=0.81 LDPC code outperforms R=0.824 turbo-product code by more than 0.5 dB at BER of 10, and outperforms concatenated RS code (R=0.82) by 3 dB. The LDPC-encoded sequence was uploaded into Anritsu pattern generator via GPIB card controlled by a Personal Computer (PC). A zero-chirp MachZehnder modulator was used to generate a 10-Gb/s NRZ data stream (see Fig.1). The launch power was maintained at 0 dBm at the input of PMD emulator. The output of PMD emulator was combined with an ASE noise source output immediately prior to the preamplifier. The ASE power was controlled by variable optical attenuator (VOA, not shown in Figure) in order to provide an independent optical SNR (OSNR) adjustment at the receiver. A pre-amplified (Agilent 11982A) detector was used for direct detection and was preceded by another VOA to maintain a constant received power of -6 dBm. The sampling oscilloscope (Agilent 86105A), triggered by the data pattern, was used to acquire the received sequences, downloaded via GPIB card back to the PC which serves as an LDPC-coded turbo equalizer. Fig. 1: NRZ experimental setup 0.2 0.4 0.6 0.8 0 2 4 6 8