Temporal partitioning of data flow graphs for reconfigurable architectures

In this paper, we present the famous temporal partitioning algorithms that temporally partition a data flow graph on reconfigurable systems. We have classified these algorithms into four classes: 1 whole latency optimisation algorithms; 2 whole communication cost optimisation algorithms; 3 whole area optimisation algorithms; 4 whole latency-communication cost optimisation algorithms. These algorithms can be used to solve the temporal partitioning problem at the behaviour level.

[1]  Ranga Vemuri,et al.  Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures , 1999, IPPS/SPDP Workshops.

[2]  Christophe Bobda,et al.  Synthesis of dataflow graphs for reconfigurable systems using temporal partitioning and temporal placement , 2003 .

[3]  João M. P. Cardoso.  On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures , 2003, IEEE Trans. Computers.

[4]  Abdellatif Mtibaa,et al.  A partitioning methodology that optimizes the communication cost for reconfigurable computing systems , 2012, International Journal of Automation and Computing.

[5]  Yao-Wen Chang,et al.  Generic ILP-based approaches for time-multiplexed FPGA partitioning , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Abdellatif Mtibaa,et al.  Temporal partitioning of data flow graph for dynamically reconfigurable architecture , 2011, J. Syst. Archit..

[7]  B. Ouni,et al.  Synthesis and Time Partitioning for Reconfigurable Systems , 2004, Des. Autom. Embed. Syst..

[8]  Jhing-Fa Wang,et al.  Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Mustafa Imran Ali,et al.  Hardware / Software Partitioning and Scheduling Algorithms for Dynamically Reconfigurable Architectures , 2003 .

[10]  Mohamed Abid,et al.  An efficient list scheduling algorithm for time placement problem , 2007, Comput. Electr. Eng..

[11]  Martin D. F. Wong,et al.  Network-flow-based multiway partitioning with area and pin constraints , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  James R. Lee,et al.  Eigenvalue Bounds, Spectral Partitioning, and Metrical Deformations via Flows , 2008, 2008 49th Annual IEEE Symposium on Foundations of Computer Science.

[13]  Charles J. Alpert,et al.  Spectral Partitioning: The More Eigenvectors, The Better , 1995, 32nd Design Automation Conference.

[14]  Martin D. F. Wong,et al.  Network flow based multi-way partitioning with area and pin constraints , 1997, ISPD '97.

[15]  Steven Trimberger,et al.  Scheduling designs into a time-multiplexed FPGA , 1998, FPGA '98.

[16]  Abdellatif Mtibaa,et al.  Partitioning and scheduling technique for run time reconfigured systems , 2011, Int. J. Comput. Aided Eng. Technol..

[17]  Huiqun Liu,et al.  Network flow based circuit partitioning for time-multiplexed FPGAs , 1998, ICCAD 1998.

[18]  B. Mohar,et al.  Eigenvalues and the max-cut problem , 1990 .

[19]  Christophe Bobda,et al.  Introduction to reconfigurable computing - architectures, algorithms, and applications , 2010 .