MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.

[1]  Sujit Dey,et al.  Fault modeling and simulation for crosstalk in system-on-chip interconnects , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[2]  Sandeep K. Gupta,et al.  Enhanced crosstalk fault model and methodology to generate tests for arbitrary inter-core interconnect topology , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[3]  Mehrdad Nourani,et al.  Testing SoC interconnects for signal integrity using extended JTAG architecture , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Raminderpal Singh.  FASTHENRY: A MultipoleAccelerated 3D Inductance Extraction Program , 2002 .

[5]  Mehrdad Nourani,et al.  Built-in self-test for signal integrity , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[6]  John Lillis,et al.  Interconnect Analysis and Synthesis , 1999 .

[7]  Mattan Kamon,et al.  FASTHENRY: a multipole-accelerated 3-D inductance extraction program , 1994 .

[8]  Paolo Mauro,et al.  The Corporation of Foreign Bondholders , 2003, SSRN Electronic Journal.

[9]  Kyung Tek Lee,et al.  Test generation for crosstalk effects in VLSI circuits , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[10]  Melvin A. Breuer,et al.  Analytic models for crosstalk delay and pulse analysis under non-ideal inputs , 1997, Proceedings International Test Conference 1997.

[11]  Xiaole Xu,et al.  An approach to the analysis and detection of crosstalk faults in digital VLSI circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Mehrdad Nourani,et al.  Test pattern generation for signal integrity faults on long interconnects , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).