Exploiting VHDL-RTL features to reduce the complexity of power estimation in combinational circuits

A probabilistic method to calculate signal probabilities in order to estimate the power consumption of VHDL-RTL designs is presented. The propagation of signal probabilities is performed through the extraction of the BDD (Binary Decision Diagram) of the combinational logic. The method exploits some advantages of RTL (Register Transfer Level) designs which leads to smaller BDDs, avoiding the memory explosion caused by the signal dependences. The method is integrated in a design environment to help designers improve the quality and early explore their circuits.