Optimal clock period clustering for sequential circuits with retiming

In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing all flip-flops (FF's) and clustering the combinational part of the sequential circuit. This approach breaks the signal dependencies and assumes the positions of FF's are fixed. The positions of the FF's in a sequential circuit are in fact dynamic, because of retiming. As a result, current algorithms can only consider a small portion of the whole solution space. In this paper, we present a clustering algorithm that does not segment circuits by removing FF's. In additional, it considers the effect of retiming. The algorithm can produce clustering solutions with the optimal clock period under the unit delay model. For the general delay model, it can produce clustering solutions with a clock period provably close to optimal.

[1]  Chih-Chang Lin,et al.  Circuit partitioning with logic perturbation , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[2]  M. Shih,et al.  Circuit partitioning under capacity and I/O constraints , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[3]  Shantanu Dutt,et al.  A probability-based approach to VLSI circuit partitioning , 1996, DAC '96.

[4]  Gaetano Borriello,et al.  An evaluation of bipartitioning techniques , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[5]  Jason Cong,et al.  Acyclic Multi-Way Partitioning of Boolean Networks , 1994, 31st Design Automation Conference.

[6]  Sachin S. Sapatnekar,et al.  A fresh look at retiming via clock skew optimization , 1995, DAC '95.

[7]  Narendra V. Shenoy,et al.  Efficient Implementation Of Retiming , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[8]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[9]  Peichen Pan.  Continuous retiming: algorithms and applications , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[10]  D. F. Wong,et al.  New algorithms for min-cut replication in partitioned circuits , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[11]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[12]  Abbas El Gamal,et al.  Min-cut replication in partitioned networks , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Frank M. Johannes.  Partitioning of VLSI circuits and systems , 1996, DAC '96.

[14]  Charles J. Alpert,et al.  Spectral Partitioning: The More Eigenvectors, The Better , 1995, 32nd Design Automation Conference.

[15]  Chingwei Yeh,et al.  Circuit clustering using a stochastic flow injection method , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[17]  A. Richard Newton,et al.  A cell-replicating approach to minicut-based circuit partitioning , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[18]  Carl Sechen,et al.  Multiple FPGA Partitioning with Performance Optimization , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[19]  Eugene L. Lawler,et al.  Module Clustering to Minimize Delay in Digital Networks , 1969, IEEE Transactions on Computers.

[20]  Massoud Pedram,et al.  Delay optimal partitioning targeting low power VLSI circuits , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[21]  Martine D. F. Schlag,et al.  Spectral-Based Multi-Way FPGA Partitioning , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[22]  Rajmohan Rajaraman,et al.  Optimal Clustering for Delay Minimization , 1993, 30th ACM/IEEE Design Automation Conference.

[23]  Naveed A. Sherwani,et al.  Algorithms for VLSI Physical Design Automation , 1999, Springer US.

[24]  Robert K. Brayton,et al.  On clustering for minimum delay/ara , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[25]  C. L. Liu,et al.  Optimal clock period FPGA technology mapping for sequential circuits , 1996, DAC '96.

[26]  Dennis J.-H. Huang,et al.  On implementation choices for iterative improvement partitioning algorithms , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[27]  Chung-Kuan Cheng,et al.  Performance-driven partitioning using retiming and replication , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[28]  Chung-Kuan Cheng,et al.  Performance-Driven Partitioning Using a Replication Graph Approach , 1995, 32nd Design Automation Conference.